1. Field of the Invention
The present invention relates to a comparator for comparing absolute values of differences, and more particularly, it relates to a comparator which compares absolute values of differences between digital values.
2. Description of the Prior Art
Recentry digital signals have been employed in place of analogue signals in the field of image processing. For example, in a method for effecting contour correction, luminance signals sampled at a predetermined sampling frequency are sequentially detected from composite video signals and, then the direction in which deviation in the sampled luminance signals is larger is decided using four sampled luminance signals positioned symmetrically around a reference luminance signal. Then, contour detection is effected along the direction in which the signal deviation is larger. In this method for contour correction, a circuit for comparing absolute values of differences between sampled digital values is indispensable.
FIG. 1 is a block diagram showing an exemplary construction of a conventional circuit for comparing absolute values of differences.
With reference to FIG. 1, description is now made on the construction of the conventional circuit for comparing absolute values of differences.
The conventional circuit for comparing absolute values of differences as shown in FIG. 1 includes a first absolute value providing path and a second absolute value providing path.
The first absolute value providing path comprises:
a first subtracter 1a which receives n-bit digital values a and b and obtains the difference therebetween to supply the same to one input terminal of a multiplexer 4a and to a first inverter 2a while supplying a carry g from the most significant bit (MSB) stage of the n-bit digital value indicating the result of subtraction to the control input terminal of the multiplexer 4a,
the first inverter 2a which receives n-bit output e from the first subtracter 1a and inverts all bits thereof to supply the same to a first incrementer 3a,
the first incrementer 3a which receives the signal from the first inverter 2a and adds "1" thereto to supply the same to the other input terminal of the multiplexer 4a, and
the first n-bit multiplexer 4a which receives the signal e from the first subtracter 1a and the signal -e from the first incrementer 3a and selectively passes either the former or the latter, in response to the MSB carry output g from the first subtracter 1a, to supply the same to one input terminal of a comparator 5.
The second absolute value providing path comprises:
a second subtracter 1b which receives n-bit digital values c and d and obtains the difference therebetween to supply the same to one input terminal of a second multiplexer 4b and to a second inverter 2b while supplying a carry h from the MSB stage of the result of subtraction to a control terminal of the second multiplexer 4b,
the second inverter 2b which receives the n-bit digital signal f and inverts all bits thereof to supply the same to a second incrementer 3b,
a second incrementer 3b which receives the digital signal from the second inverter 2b and adds "1" thereto to supply the same to the other input terminal of the second multiplexer 4b, and
the second multiplexer 4b which receives the digital signals from the second subtracter 1b and the second incrementer 3b and selectively passes either the former or the latter, in response to the MSB carry output g from the second subtracter 1b, to supply the same to the other input terminal of the comparator 5.
The comparator 5 compares digital signals k and l from the first and second multiplexers 4a and 4b to output a digital signal m corresponding to the result of comparison.
Description is now made on the operation of the conventional circuit as shown in FIG. 1.
The first subtracter 1a receives the n-bit binary-coded digital values a and b and performs subtraction of (a-b) to output the result e of subtraction, while supplying the carry output g from the MSB stage of the result e of subtraction to the control terminal of the first multiplexer 4a. The first inverter 2a receives the result e of subtraction from the first subtracter 1a to supply the signal obtained by inverting all bits thereof to the first incrementer 3a. The first incrementer 3a adds "1" to the digital value from the first inverter 2a to supply the same to the other input terminal of the first multiplexer 4a.
Namely, one input terminal of the multiplexer 4a directly receives the result e of subtraction while the other input terminal thereof receives the digital value obtained by inverting the sign of the result e of subtraction.
With the MSB carry output g from the first subtracter 1a serving as the sign bit, (n+1)-bit digital data formed of (g+e) represents the result of subtraction (a-b) in an offset binary-coded digital value.
The MSB carry output g is "1" when the result e of subtraction (i.e., a-b) in the subtracter 1a is positive and is "0" when the result e of subtraction is negative.
When the MSB carry output g from the first subtracter 1a is "1", the first multiplexer 4a receiving the MSB carry output g in its control input terminal selects the result e of subtraction since (a-b)&gt;0, to supply the same to one input terminal of the comparator 5. When, to the contrary, the MSB carry output g from the first subtracter 1a is "0", it indicates (a-b)&lt;0 and hence the first multiplexer 4a selects the sign-inverted value (b-a) from the first incrementer 3a to supply the same to one input terminal of the comparator 5. Thus, the first multiplexer 4a always supplies the absolute value data k of (a-b) to one input terminal of the comparator 5.
The operation of the second absolute value providing path is identical to that of the first absolute value providing path. Namely, in response to the carry output h from the MSB stage of the result f of subtraction of the n-bit binary-coded digital values c and d, the second multiplexer 4b outputs (c-d) when the carry output h is "1" and outputs (-c+d) when the carry output h is "0". Thus, the second multiplexer 4b always supplies the absolute value data l of (c-d) to the other input terminal of the comparator 5.
The comparator 5 compares the absolute value data k from the first multiplexer 4a with the absolute value data l from the second multiplexer 4b, to output the result m of comparison.
FIG. 2 illustrates an exemplary construction of the comparator 5 used in FIG. 1.
Referring to FIG. 2, the comparator is formed by a number n of cascade-connected full adders 6 each having only a carry output and no sum output. Each full adder 6 receives a bit value x.sub.i (i=1 to n) in one input terminal thereof while receiving a bit value y.sub.i (i=1 to n) through an inverter 2. The full adder 6 for the least significant bit (LBS) is supplied with "1" in its carry input terminal, while carry output p from the full adder 6 for the most significant bit (MSB) serves as the output m of the comparator 5. The operation of the comparator is now described with reference to FIG. 2. It is assumed here that X={x.sub.i } and Y={y.sub.i } for convenience of illustration.
The binary digital values X.sub.i are supplied to the respective one input terminals of the full adders 6. The binary digital values y.sub.i are supplied to the respective other input terminals of the full adders 6 through the inverters 2, while the full adder 6 for the LSB is supplied with "1" in its carry input terminal. Thus, the n full adders 6 calculate (X-Y), and the full adder 6 for the MSB supplies the carry output p thereof.
If carry p=1, then X.gtoreq.Y; and
if carry p=0, then X&lt;Y.
Thus, when the carry output p is employed as the result m of comparison in the comparator 5, supplied is the binary digital value according to the values of .vertline.a-b.vertline. and .vertline.c-d.vertline..
The conventional circuit for comparing absolute values of differences is in the aforementioned construction, whereby a large number of components such as multiplexers, incrementers and the like are required, leading to disadvantages such as increase in scale of the circuit.